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This release consists of two repositories
(1) openhwgroup/cv32e40p
CV32E40P is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements the RV32IM[F]C instruction set architecture, and the Xpulp custom extensions for achieving higher code density, performance, and energy efficiency [1], [2]. It started its life as a fork of the OR10N CPU core that is based on the OpenRISC ISA. Then, under the name of RI5CY, it became a RISC-V core (2016), and it has been maintained by the PULP platform team until February 2020, when it has been contributed to OpenHW Group.
(2) openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
1.0
First release after moving the project to the Eclipse Foundation.
This release includes content from the following Git repositories.
- https://github.com/openhwgroup/core-v-verif.git
- https://github.com/openhwgroup/cv32e40p.git