OpenHW Group CORE-V Cores 1.0 Release Review

Type
Release
State
Successful
End Date of the Review Period

Reviews run for a minimum of one week. The outcome of the review is decided on this date. This is the last day to make comments or ask questions about this review.

Project
OpenHW Group CORE-V Cores
Release

1.0

Description

First release after moving the project to the Eclipse Foundation.

This release includes content from the following Git repositories.

  • https://github.com/openhwgroup/core-v-verif.git
  • https://github.com/openhwgroup/cv32e40p.git
Conforms To UI/UX Guidelines
Not verified

This release consists of two repositories

(1) openhwgroup/cv32e40p

CV32E40P is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements the RV32IM[F]C instruction set architecture, and the Xpulp custom extensions for achieving higher code density, performance, and energy efficiency [1], [2]. It started its life as a fork of the OR10N CPU core that is based on the OpenRISC ISA. Then, under the name of RI5CY, it became a RISC-V core (2016), and it has been maintained by the PULP platform team until February 2020, when it has been contributed to OpenHW Group.

(2) openhwgroup/core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.