Creation Review

Type
Creation
State
Successful
End Date of the Review Period

Reviews run for a minimum of one week. The outcome of the review is decided on this date. This is the last day to make comments or ask questions about this review.

Project
OpenHW Group CORE-V Cores
Proposal

OpenHW Group CORE-V Cores

Wednesday, January 29, 2020 - 18:11 by Mike Thompson
Basics
This proposal is in the Project Proposal Phase (as defined in the Eclipse Development Process) and is written to declare its intent and scope. We solicit additional participation and input from the community. Please login and add your feedback in the comments section.
Project
OpenHW Group CORE-V Cores
Parent Project
OpenHW Group
Proposal State
Created
Background

CORE-V is a family open-source of microprocessor cores based on the RISC-V Instruction Set Architecture.  The first two members of the family, CV32E and CV64A are derived from open-source implementations created by the PULP-Platform team at ETH Zurich.

Scope

OpenHW Group CORE-V Cores produces industrial quality fully documented and verified implementations of the CV32E and CV64A

Description

The tangible products produced by OpenHW Group CORE-V Cores includes:

  • Complete documentation: micro-architecture and a user manual.
  • Implementation: RTL model and synthesis scripts for both ASIC and FPGA implementations.
  • Verification: both dynamic (simulation) and static (formal) verification environments.
Licenses
Apache License, Version 2.0
Eclipse Public License 2.0
Legal Issues

All products produced by the OpenHW Group shall be covered by one or more of:

  • Solderpad Hardware License, SHL v2.0
  • Apache License v2.0
  • Eclipse Public License, v2.0

SHL is a permissive license implemented as a 'wrapper' around Apache v2.0.  See https://solderpad.org/licenses/SHL-2.0 for more information.

Note that some artifacts may be covered by SHL v0.51 or soley Apache v2.0 only (not SHL).

Why Here?

The open-source RISC-V Instruction Set Architecture created by UC Berkley and now maintained by the RISC-V Foundation inspired a growing community of open source hardware development.  Some believe that RISC-V will do for hardware what Linux has done for software.  The OpenHW Group is committed to this open source future and the Eclipse Foundation is a natural home for OpenHW projects.

Project Scheduling

The OpenHW Group is working to "tape-out" (release a build for silicon fabrication) in the second half of 2020.  A more detailed schedule can be found at https://github.com/openhwgroup/core-v-docs/tree/master/cores.

People
Project Leads
Rick O'Connor
Committers
Mike Thompson
Davide Schiavone
Jim Parisien
Rick O'Connor
Mentors
Wayne Beaton
Source Code
Initial Contribution

The CV32E is derived from the PULP-Platform RI5CY project: https://github.com/pulp-platform/riscv

The CV64A is derived from the PULP-Platform Ariane project: https://github.com/pulp-platform/ariane

OpenHW Group has started development of CORE-V.  The documentation is on GitHub at https://github.com/openhwgroup/core-v-docs and the code base is at https://github.com/openhwgroup/core-v-verif.

Source Repository Type
GitHub
Source Repositories
https://github.com/openhwgroup/core-v-docs
https://github.com/openhwgroup/core-v-verif