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OpenHW Group CORE-V Cores produces industrial quality fully documented and verified implementations of the CV32E and CV64A
The tangible products produced by OpenHW Group CORE-V Cores includes:
- Complete documentation: micro-architecture and a user manual.
- Implementation: RTL model and synthesis scripts for both ASIC and FPGA implementations.
- Verification: both dynamic (simulation) and static (formal) verification environments.
The open-source RISC-V Instruction Set Architecture created by UC Berkley and now maintained by the RISC-V Foundation inspired a growing community of open source hardware development. Some believe that RISC-V will do for hardware what Linux has done for software. The OpenHW Group is committed to this open source future and the Eclipse Foundation is a natural home for OpenHW projects.
The CV32E is derived from the PULP-Platform RI5CY project: https://github.com/pulp-platform/riscv
The CV64A is derived from the PULP-Platform Ariane project: https://github.com/pulp-platform/ariane
OpenHW Group has started development of CORE-V. The documentation is on GitHub at https://github.com/openhwgroup/core-v-docs and the code base is at https://github.com/openhwgroup/core-v-verif.
All products produced by the OpenHW Group shall be covered by one or more of:
- Solderpad Hardware License, SHL v2.0
- Apache License v2.0
- Eclipse Public License, v2.0
SHL is a permissive license implemented as a 'wrapper' around Apache v2.0. See https://solderpad.org/licenses/SHL-2.0 for more information.
Note that some artifacts may be covered by SHL v0.51 or soley Apache v2.0 only (not SHL).
The OpenHW Group is working to "tape-out" (release a build for silicon fabrication) in the second half of 2020. A more detailed schedule can be found at https://github.com/openhwgroup/core-v-docs/tree/master/cores.