CORE-ET Silicon Platform is a collection of open building blocks (from multi-core silicon to scalable inference frameworks) suitable for building end-to-end solutions for AI at the edge. ETSP is developed along with industrial and academic partners and is open source.
CORE-ETSP provides a platform for running fast and low-power AI inference workloads at the edge.
In-scope :
- Many-core 64-bit (with vector/SIMD extensions) low-power CPU design including NoC and on-chip MRAM
- Multiple interfaces for use both as an accelerator board, and as a stand-alone system
- Reference Designs
- A full-featured emulator that allows rapid evolution of the architecture
- Development platform for building and running inference frameworks
- Comprehensive set of tools for porting existing frameworks
- Documentation for all layers
CORE-ETSP combines many-core RISC-V-based RTL with MRAM and thus creating a basis for the next generation ET Silicon Platform design. It can be deployed either in a traditional configuration with the host CPU accessing ETSP as an Intelligent RAM (replacing SRAM and Flash) via Hyperbus OR as a self-hosted array of microcontrollers (with or without a host CPU).
When combined with the development platform (composed of various open upstream components), ETSP platform is a comprehensive solution for fast and low-power AI inference workloads at the edge. Multiple verticals and embedded AI systems in manufacturing, robotics and drones, and security systems may benefit from ETSP.
No problem foreseen to pass the IP on to the Eclipse Foundation. The final project's name might change before the project creation.
The Eclipse foundation brings strong guarantees regarding the impartiality, governance, IP and perenniality of the project that are extremely important for our industry and academic partners and for the community in general.
The project aims to develop a general-purpose many-core platform focused on the problems of AI inference at the edge, enabling use-cases of the rapidly evolving AI applications across multiple industries. Currently, many such use cases in manufacturing, robotics, aviation, and agriculture, are prohibitive, not only due to costly infrastructure, but also huge power demand. This value proposition is still relatively unclaimed or not claimed by existing GPU-based platforms, which are still tailored for the data center. Thus, the first innovation of the project is to address within a single platform the entire chain of design and deployment of AI inference at the edge. Beyond, opening everything down to RTL, ETSP’s long term goals include:
- Give developers the freedom to hack, profile, break, and improve.
- Enable co-development of AI software and hardware
- Avoid vendor lock-in by supporting open-source chip-design tooling (including collaborations with Zero ASIC and chiplet/open-tooling work
- Enable community-driven architectures that evolve faster than proprietary ones.
We propose an annual cycle of major releases:
April 2026 : 1st release of the [open source] platform
- Detailed Architecture Document
- Datasheet(s)
- Programmers’ Reference Manual
- Documentation, tutorials and examples of implemented functions;
- Functional roadmap of the next release.
April 202X: N+1th major release of the platform. [open source]
Once registered, these folks will become the project leads.
- Gianluca Guida <gianluca@nekko.ai>
- Allen Rush <allen@nekko.ai>
- Doug Smith <doug@nekko.ai>
- Michael Jaggers <michael@nekko.ai>
- Roman Shaposhnik <roman@nekko.ai>
- Detailed Architecture Document
- Datasheet(s)
- Programmers’ Reference Manual
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Love it! Lets do it!
Submitted by Florian Wohlrab on Thu, 02/12/2026 - 02:19
Cool an AI SoC and all OpenSource: I like it!
Especially having a real chip will be super cool and enable even more testing and collaboration!
Looking forward to get that project started!