CORE-ETSP combines many-core RISC-V-based RTL with MRAM and thus creating a basis for the next generation ET Silicon Platform design. It can be deployed either in a traditional configuration with the host CPU accessing ETSP as an Intelligent RAM (replacing SRAM and Flash) via Hyperbus OR as a self-hosted array of microcontrollers (with or without a host CPU).
When combined with the development platform (composed of various open upstream components), ETSP platform is a comprehensive solution for fast and low-power AI inference workloads at the edge. Multiple verticals and embedded AI systems in manufacturing, robotics and drones, and security systems may benefit from ETSP.
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Member companies supporting this project over the last three months.