OpenHW CV-Sargantana is a research-oriented, implementation-ready application-class core. The simplicity and modularity of CV-Sargantana can help bridge the gap between academic research and real-world applications. Register renaming and out-of-order writeback ease the integration of tighty-coupled accelerators (like custom ISA extensions) while the AXI interfaces that connect to higher levels of the memory hierarchy allow the integration of loosely-coupled accelerators.
OpenHW CV-Sargantana can run RTL simulations with the use of open-source tools. It can also be synthesized targeting an FPGA or ASIC design. Verification is done at the RTL simulation level with an environment built on the Universal Verification Methodology (UVM). The core is co-simulated against a cycle-accurate execution trace generated by the Spike RISC-V instruction set simulator.
The content of this open source project is received and distributed under the license(s) listed above. Some source code and binaries may be distributed under different terms. Specific license information is provided in file headers and in NOTICE files distributed with the project's binaries.
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