This proposal has been approved and the OpenHW CV-Sargantana project has been created.
Visit the project page for the latest information and development.

Go to Project

OpenHW CV-Sargantana

Thursday, July 2, 2026 - 10:21 by Narcís Rodas
Basics
This proposal is in the Project Proposal Phase (as defined in the Eclipse Development Process) and is written to declare its intent and scope. We solicit additional participation and input from the community. Please login and add your feedback in the comments section.
Project
OpenHW CV-Sargantana
Parent Project (optional)
OpenHW
Proposal State
Created
Background

CV-Sargantana is a 64-bit processor based on RISC-V that implements the RV64GBH ISA plus partial RVV 1.0 support (full ISA string RV64GBH_Zicntr_Zicond_Zicsr_Zihpm_Zfa_Zfhmin_Zvbb_Zvfhmin_
Zicbom_Zicbop_Zicboz_Smcntrpmf_Sscofpmf_Sha_Sdext). It started development around 2020 at BSC and was released as open-source in GitHub in November 2023. The current developers and maintainers are the High Performance Domain Specific Architectures (HPDSA) and Verification teams from BSC. Earlier versions of CV-Sargantana have been part of 3 tape-outs (Sargantana 2022, Kameleon and Cinco Ranch) with other RISC-V cores from the BSC.

CV-Sargantana is an in-order core with a single-issue 7-stage pipeline. It features out-of-order writeback and register renaming, and it is connected to the OpenHW CV-HPDcache. 

CV-Sargantana is also part of REPTILES, an open-source multi-core framework based on OpenPiton (CV-Mesh). It supports booting Linux and has been tested in FPGA emulation.

Scope

OpenHW CV-Sargantana is a Linux-capable RISC-V core that is planned to be compatible with the RISC-V RVA23S64 profile by 2027. One of its design goals is to facilitate the design and development of domain-specific accelerators on top of CV-Sargantana. 

OpenHW CV-Sargantana will include the full RTL of the core, single module testbenches and a High-Level Architecture Specification document. The plan is to improve the documentation by making a detailed User Manual and reach a TRL-5.

Description

OpenHW CV-Sargantana is a research-oriented, implementation-ready application-class core. The simplicity and modularity of CV-Sargantana can help bridge the gap between academic research and real-world applications. Register renaming and out-of-order writeback ease the integration of tighty-coupled accelerators (like custom ISA extensions) while the AXI interfaces that connect to higher levels of the memory hierarchy allow the integration of loosely-coupled accelerators.

OpenHW CV-Sargantana can run RTL simulations with the use of open-source tools. It can also be synthesized targeting an FPGA or ASIC design. Verification is done at the RTL simulation level with an environment built on the Universal Verification Methodology (UVM). The core is co-simulated against a cycle-accurate execution trace generated by the Spike RISC-V instruction set simulator.

Licenses
Solderpad Hardware Licence, Version 2.1
Why Here?

One of our goals is to make CV-Sargantana the reference design for an european multi-core platform for accelerator development. We believe making CV-Sargantana a part of OpenHW will foster collaborations with other members and partners. We also believe making this will greatly improve its discoverability.

Future Work

With the release of CV-Sargantana v3.1, we are only missing a few RISC-V extensions to support the full RVA23S64 profile (more specifically, the C, full RVV 1.0, Zicclsm, Zicond, Zimop, Zcmop, Zcb, Zawrs, Svpbmt, Svinval, Svnapot and Sstc extensions). In the next months, we plan to add the support for the remaining extensions to be fully RVA23-compliant.

The timeline of future updates is as follows:

  • Q4 2026
    • Complete the support for full RVV 1.0
    • Add support for C extension
  • Q1 2027
    • Publish FPGA tutorial
    • Document accelerator interfaces (both for tightly-coupled and loosely-coupled)
    • Document contribution workflow
  • Q2 2027
    • Implement all remaining RVA23S64 extensions
    • Publish architectural compliance test results and known limitations
Project Scheduling

We will periodically release a new version of the CV-Sargantana core (around 2 releases per year). 

The timeline of future updates is as follows:

  • Support for full RVV 1.0 and C extensions (Q4 2026)
  • Improvement of documentation (Q1 2027)
  • Implementation and verification of all mandatory RVA23S64 extensions (Q2 2027)
People
Project Leads
Narcís Rodas
Miquel Moreto
Committers
Narcís Rodas
Arnau Bigas
Miquel Moretó
Mike Thompson
Raúl Gilabert
Marc Marcos
Source Code
Initial Contribution

CV-Sargantana (a clone of the Sargantana GitHub repo without history, existing issues, pull requests and releases). The core_tile and Openpiton integrations are not included.

Source Repository Type
GitHub
Source Repositories
https://github.com/bsc-loca/sargantana

Submitted by Mike Thompson on Wed, 08/05/2026 - 11:17

Hi Narcis, this is a terrific project proposal.  It would be useful to specify the project's verification goals for each of the planned releases.  If you have any questions about that, please rearch out to me on MatterMost.

My Eclipse ID is mthompson7k1.